During the fabrication of integrated circuits, chemical-mechanical polishing (CMP) processes are typically utilized in order to form planar surfaces for a semiconductor device structure. Polishing compositions (also known as polishing slurries) typically contain an abrasive material in a liquid carrier along with other chemical components and are applied to a surface by contacting the surface with a rotating polishing pad saturated with the polishing composition. The chemical components chemically modify at least some of the substrate material to promote physical removal by the combination of the abrasive and the polishing pad. In some instances, the chemical components may also promote removal of material.
In microelectronic structures such as CMOS transistors and NAND gates, substrate features such as metal gates are often overlaid with a layer of a dielectric material, which is then planarized to expose the metal gates separated by the dielectric material. Prior to planarization, the substrate surface is characterized by “high” areas overlying the gates and “low” areas which lie between the gates. Initially, the high areas are removed more quickly than the low areas because the pressure exerted by the polishing pad is directed primarily at the high areas. As the planarization proceeds, due in part to the deformability of the polishing pad, the low areas experience material removal, resulting in what is referred to as trench loss.
Polishing compositions comprising ceria abrasives have been explored for polishing such dielectric-layered substrates. While dielectric removal rates can be improved, trench loss becomes increasing significant as the removal rate increases. Thus, there is a need in the art for dielectric polishing compositions exhibiting good removal rates while also exhibiting reduced trench loss.